? 19 94 fa i r ch i l d s e m i con duct o r c o rp or ati o n w w w . f ai r c hi l d se mi .c om fe br u a r y 20 09 7 4 l v xc32 45 ? 8-bit dual supply co nfigura b le v o lt age interfac e t r a n s c e i ve r wi t h 3 - st a t e output s 74 l v xc 32 4 5 8 - bit du a l supp l y c onfi g ur able v o lt age i n ter f ace t r ansce ive r wi th 3-s t a t e output s fe atur es b i di r e cti o na l i n te rfac e b e tw e en 3v an d 3 v - t o- 5v bu ses co n t r o l in p u ts co m p a t ib le with t t l le ve l o u tp ut s sour ce/ s ink u p to 24 m a g uar ant eed si mu l t an eo us sw i t ch i ng n o i s e l e vel a n d dy n a m i c t h r e s h ol d p e r f or ma n c e f l e x ib le v cc b op er a t i n g ra ng e allo ws b po r t a n d v ccb to f l o a t sim u ltan eou sly whe n oe is high f u n c tio n a lly co m p a t ib le with th e 7 4 se r i e s 2 4 5 g e n e r a l d e s c r ip t i o n t he l v x c 3 2 4 5 i s a 24 -p i n du al - s upp l y , 8- bi t c onf i g ur abl e vol t ag e i n terf ace tra n sce i v er sui t ed for p c mc ia and ot her re al t i me con f igu r ab le i/o app licatio ns. t h e v cca pi n acc epts a 3 v sup p l y l e v e l . t he a p o rt i s a de di cat ed 3 v po rt. th e v cc b pi n acce pts a 3v -to - 5v s upp l y l e ve l . t h e b p o r t i s con f i g u r ed t o trac k th e v cc b s u p p ly le ve l r e sp e c - tive ly . a 5 v le ve l o n th e v cc p i n will co n f ig u r e t h e i/ o p i n s at a 5v l e vel a n d a 3v v cc will co n f ig u r e th e i/ o p i n s a t a 3v l e vel . the a p o r t sh oul d i n te rfa c e w i t h a 3v ho st sy stem a n d t h e b p o r t to th e c a r d slo t s. t h is d e vice will a llo w th e v cc b v o lt a ge sou r ce pin an d i/o pins on th e b p o rt to floa t wh e n o e i s h i g h . t h i s f e a t ur e i s n e c e s s a r y to bu f f er da t a to and fro m a p c mcia so cket that per mits p c mcia ca rd s to be i n se rted an d r e m o ve d d u ri n g n o rm al o p e r ati o n. or deri ng code: de vi ce s a l so a v a i l a b l e i n t a p e a n d re e l . s p e c i fy b y a p p e n d i n g su f f i x l e t t e r ? x ? to th e o r d e r i n g co d e . lo gic sym b o l / s pi n des c ri pti ons connect ion dia g ram/s or de r n u m b er p a ck age n u m b er p ack ag e d e scr ip tio n 74 l v x c 3 245 w m m2 4b 22 4-l ead s m a l l ou tl i ne inte gra t ed c i r cu i t ( s o i c ) , je d e c ms - 013 , 0 . 300 " w i de 74 l v x c 3 245 qs c m qa 24 24 -le ad qua r te r s i ze out l i ne p a ckag e ( q s o p ) , je d e c mo -13 7 , 0.1 50" w i de 74 l v x c 3 245 mt c m tc 2 4 24 -le ad th i n s h r i nk s m al l ou tl i n e p a cka ge (t s s o p ), je d e c m o - 153 , 4 . 4m m w i d e pi n n a m e s d es c r i p t i on oe o u tp ut e n abl e inp u t t/ r t r an sm i t /r ece i ve i npu t a 0 ?a 7 s i de a in puts or 3- s t a t e ou tpu t s b 0 ?b 7 s i de b in puts or 3- s t a t e ou tpu t s im pl e m e n t s proprietary e m i r e d u cti o n ci r c ui tr y
www.fairchildsemi.com 2 74lvxc3245 ? 8-bit dual supply configurable volt age interface transceiver with 3-state outputs truth table/s h = = =
3 www.fairchildsemi.com 74lvxc3245 ? 8-bit dual supply configurable volt age interface transceiver with 3-state outputs absolute maximum ratings (note 1) recommended operating conditions (note 2) note 1: the ?absolute maximum ratings? are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum ratings. the ?recommended operating conditions? table will define the conditions for actual device operation. note 2: the a port unused pins (inputs or i/os) must be held high or low. they may not float. dc electrical characteristics supply voltage (v cca , v ccb ) ? + ? + ? + ? + ? + ? + = = ? + ? ? = ? = ? = ? = ? = ? = ? = ? = ? = ? = = = = = = = =
www.fairchildsemi.com 4 74lvxc3245 dc electrical characteristics (continued) note 3: worst case package. note 4: max number of outputs defined as (n). data inputs are driven 0v to v cc level; one output at gnd. note 5: max number of data inputs (n) switching. (n ? 1) inputs switching 0v to v cc level. input-under-test switching: v cc level to threshold (v ihd ), 0v to threshold (v ild ), f = 1 mhz. symbol parameter v cca v ccb t a = 25 ct a = ? 40 c to + 85 c units conditions (v) (v) typ guaranteed limits i oza maximum 3-state 3.6 3.6 0.5 5.0 a v i = v il , v ih , output leakage 3.6 5.5 0.5 5.0 oe = v cca @ a n v o = v cca , gnd i ozb maximum 3-state 3.6 3.6 0.5 5.0 a v i = v il , v ih , output leakage 3.6 5.5 0.5 5.0 oe = v cca @ b n v o = v ccb , gnd ? i cc maximum b n 3.6 5.5 1.0 1.35 1.5 ma v i = v ccb ? 2.1v i cc /input all inputs 3.6 3.6 0.35 0.5 v i = v cc ? 0.6v i cca1 quiescent v cca a n = v cca or gnd supply current 3.6 open 5 50 ab n = open, oe = v cca , as b port floats t/r = v cca , v ccb = open i cca2 quiescent v cca 3.6 3.6 5 50 a a n = v cca or gnd, supply current 3.6 5.5 5 50 b n = v ccb or gnd, oe = gnd, t/r = gnd i ccb quiescent v ccb 3.6 3.6 5 50 a a n = v cca or gnd, supply current 3.6 5.5 8 80 b n = v ccb or gnd, oe = gnd, t/r = v cca v olpa quiet output 3.3 3.3 0.8 v (note 3)(note 4) maximum dynamic 3.3 5.0 0.8 v olpb v ol 3.3 3.3 0.8 v (note 3)(note 4) 3.3 5.0 1.5 v olva quiet output 3.3 3.3 ? 0.8 v (note 3)(note 4) minimum dynamic 3.3 5.0 ? 0.8 v olvb v ol 3.3 3.3 ? 0.8 v (note 3)(note 4) 3.3 5.0 ? 1.2 v ihda minimum high 3.3 3.3 2.0 v (note 3)(note 5) level dynamic 3.3 5.0 2.0 v ihdb input voltage 3.3 3.3 2.0 v (note 3)(note 5) 3.3 5.0 3.5 v ilda maximum low 3.3 3.3 0.8 v (note 3)(note 5) level dynamic 3.3 5.0 0.8 v ildb input voltage 3.3 3.3 0.8 v (note 3)(note 5) 3.3 5.0 1.5
5 www.fairchildsemi.com 74lvxc3245 ac electrical characteristics note 6: typical values at v cca = 3.3v, v ccb = 5.0v @ 25 c. note 7: typical values at v cca = 3.3v, v ccb = 3.3v @ 25 c. note 8: skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of th e same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). parameter guaranteed by design. capacitance note 9: c pd is measured at 10 mhz. symbol parameter t a = + 25 ct a = ? 40 c to + 85 ct a = + 25 ct a = ? 40 c to + 85 c units c l = 50 pf c l = 50 pf c l = 50 pf c l = 50 pf v cca = 2.7v?3.6v v cca = 2.7v?3.6v v cca = 2.7v?3.6v v cca = 2.7v?3.6v v ccb = 4.5v?5.5v v ccb = 4.5v?5.5v v ccb = 3.0v?3.6v v ccb = 3.0v?3.6v min typ max min max min typ max min max (note 6) (note 7) t phl propagation delay 1.0 4.8 8.0 1.0 8.5 1.0 5.5 8.5 1.0 9.0 ns t plh a to b 1.0 3.9 6.5 1.0 7.0 1.0 5.2 8.0 1.0 8.5 t phl propagation delay 1.0 3.8 6.5 1.0 7.0 1.0 4.4 7.0 1.0 7.5 ns t plh b to a 1.0 4.3 7.5 1.0 8.0 1.0 5.1 7.5 1.0 8.0 t pzl output enable time 1.0 4.7 8.0 1.0 8.5 1.0 6.0 9.0 1.0 9.5 ns t pzh oe to b 1.0 4.8 8.5 1.0 9.0 1.0 6.1 9.5 1.0 10.0 t pzl output enable time 1.0 5.9 9.5 1.0 10.0 1.0 6.4 10.0 1.0 10.5 ns t pzh oe to a 1.0 5.4 9.0 1.0 9.5 1.0 5.8 9.0 1.0 9.5 t phz output disable time 1.0 4.0 8.0 1.0 8.5 1.0 6.3 9.5 1.0 10.0 ns t plz oe to b 1.0 3.8 7.5 1.0 8.0 1.0 4.5 8.0 1.0 8.5 t phz output disable time 1.0 4.6 9.5 1.0 10.0 1.0 5.2 9.5 1.0 10.0 ns t plz oe to a 1.0 3.1 6.5 1.0 7.0 1.0 3.4 6.5 1.0 7.0 t oshl output to output t oslh skew (note 8) 1.0 1.5 1.5 1.0 1.5 1.5 ns data to output symbol parameter typ units conditions c in input capacitance 4.5 pf v cc = open c i/o input/output capacitance 10 pf v cca = 3.3v v ccb = 5.0v c pd power dissipation a b50pfv ccb = 5.0v capacitance (note 9) b a40pfv cca = 3.3v
www.fairchildsemi.com 6 74lvxc3245 power up considerations to insure the system does not experience unnecessary i cc current draw, bus contention, or oscillations during power up, the following guidelines should be adhered to (refer to table 1): power up the control side of the device first. this is the v cca side. oe should ramp with or ahead of v cca . this will help guard against bus contention. the transmit/receive control pin (t/r ) should ramp with v cca , this will ensure that the a port data pins are con- figured as inputs. with v cca receiving power first, the a i/o port should be configured as inputs to help guard against bus contention and oscillations. a side data inputs should be driven to a valid logic level. this will prevent excessive current draw. the above steps will ensure that no bus contention or oscil- lations, and therefore no excessive current draw occurs during the power up cycling of these devices. these steps will help prevent possible damage to the translator devices and potential damage to other system components. table 1. low voltage translator power up sequencing table please reference application note an-5001 for more detailed information on using fairchild ? s lvx low voltage dual supply cmos translating transceivers. configurable i/o application for pcmcia cards block diagram the lvxc3245 is a 24-pin dual supply device well suited for pcmcia configurable i/o applications. ideal for low power notebook designs, the lvxc3245 consumes less than 1 mw of quiescent power in all modes of operation. the lvxc3245 meets all pcmcia i/o voltage require- ments at 5v and 3.3v operation. by tying v ccb of the lvxc3245 to the card voltage supply, the pcmcia card will always experience rail to rail output swings, maximizing the reliability of the interface. the v cca pin on the lvxc3245 must always be tied to a 3v power supply. this voltage connection provides internal references needed to account for variations in v ccb . when connected as in the figure above, the lvxc3245 meets all the voltage and current requirements of the isa bus stan- dard (ieee p996). device type v cca v ccb t/r oe a side i/o b side i/o floatable pin allowed 74lvxc3245 3v 3v to 5.5v ramp ramp logic outputs yes, v ccb and b (power up 1st) configurable with v cca with v cca 0v or v cca i/o ? s w/ oe high
7 www.fairchildsemi.com 74lvxc3245 physical dimensions inches (millimeters) unless otherwise noted 24-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide package number m24b 24-lead quarter size outline package (qsop), jedec mo-137, 0.150" wide package number mqa24
www.fairchildsemi.com 8 74lvxc3245 8-bit dual supply configurable voltage interface transceiver with 3-state outputs physical dimensions inches (millimeters) unless otherwise noted (continued) 24-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package number mtc24 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
9 www.fairchildsemi.com 74lvxc3245 ? 8-bit dual supply configurable volt age interface transceiver with 3-state outputs
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